New SoCs devices for mobile phones, automobiles, Intelligent Edge nodes and sensors, big-data compute and storage are adopting AI/ML technology. This is driving new memory architectures and photonic interfaces. Because of single nanometer process nodes, specialized new IPs require analysis down to the nanometer and atomic levels. To address the span from architecture to device physics, design technology co-optimization (DTCO) using TCAD solutions, along with proven design IPs are needed for next-generation SoC design. The current state-of-the-art and what are the new challenges that need to be addressed will be presented.