The goal of this presentation is to uncover all the various techniques used by designers in the industry to make chips energy efficient. Some of the design changes that are incorporated to reduce energy impose a challenge when functionally validating the design and sign-off. How do we preserve the energy reduction seen at architectural level all the way to transistors using the existing ASIC methodology? How do we measure energy/power at each stages? How do we correlate these to Silicon? This session will provide a complete methodology including Functional Verification, Logical/Physical implementation and Signoff for an energy efficient design.